[SOLVED] VHDL: formal port ‘portName’ has no actual or default value


This Content is from Stack Overflow. Question asked by DeReK YuEn

I’m trying to simulate my VHDL component in Vivado and i’m receiving a compilation error: “formal generic ‘n’ has no actual or default value”. I would appreciate any advice or solution to this error.

I have seen the issue VHDL: formal port ‘portName’ has no actual or default value and my error, although similar, does not seem related.

entity bit_tester is 
generic (N : integer);
port(in1 : in bit_vector (N-1 downto 0);
    out1 : out bit;
    out2 :out bit;
    out3 :out bit);
end bit_tester;

architecture behavioral of bit_tester is


IEEE Std 1076-2008

11.7 Component instantiation statements

component_instantiation_statement ::=
    instantiation_label :
            [ generic_map_aspect ]
            [ port_map_aspect ] ; 


generic_map_aspect ::=     
   generic map (generic_association_list ) 

You have a semicolon too much at the end of generic map(BIT_DEPTH,INPUT_CLK,FREQ);, for this reason, it is not seeing the mapping of the ports and giving you the error.
To solve the error just delete that semicolon:

dev_to_test: PWM
        generic map(BIT_DEPTH,INPUT_CLK,FREQ)
        port map(Pwm_Out,Duty_Cycle,Clk,Enable);

PS: to reduce the risk of design errors, it is good practice to use named association in port and generic mapping instead of positional.

This Question was asked in StackOverflow by chainastole and Answered by Giampietro Seu It is licensed under the terms of CC BY-SA 2.5. - CC BY-SA 3.0. - CC BY-SA 4.0.

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